expand all

To design an FFT 1536 block, radix-3 decimation-in-time (DIT) algorithm is
implemented. The input sequence *x(n)* for all *n =
{0,1,2....1535}* is divided into three DIT sequences, *x(3n), x(3n+1),
x(3n+2)* for all *n = {0,1,2....511}*.

This equation defines FFT 1536 computation of a given sequence
*x(n)*.

The equation can be implemented by dividing it into three parts, where *P(k),
Q(k), R(k)* are the N/3 (FFT 512) point FFT of *x(3n), x(3n+1), and
x(3n+2)*, respectively. Here, *N = 1536, and k =
0,1,2,.....,511*.

This diagram shows the internal architecture of the block and how the input sequence
streams through the components of the block.

The input sequence *x(n)* is demultiplexed into three DIT sequences,
*x(3n), x(3n+1), x(3n+2)*, each of length 512. Three first-input
first-output (FIFO) memories store these sequences. These DIT sequences are serialized and
streamed through the **FFT 512** block.

### Latency

This image shows the output waveform of the block when operated with default
configuration parameters. The block provides output data after a latency of 3180 clock
cycles. The length of the output data between `start`

(**Ctrl.(1)**) and `end`

(**Ctrl.(2)**)
output control signals is 1536 clock cycles.

### Performance

The performance of the synthesized HDL code varies with your target and synthesis
options. This table shows the resource and performance data synthesis results of the block
with default configuration parameters, along with normalization feature enabled, and with an
input data in `fixdt(1,17,15)`

format. The generated HDL is targeted to
Xilinx^{®}
Zynq^{®} XC7Z045-FFG900-2 FPGA board. The design
achieves a clock frequency of 355 MHz.

Resource | Number Used |
---|

LUTs | 7330 |

Registers | 9325 |

Block RAMs | 18 |

DSPs | 36 |